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Design CPU Core
System Clock
The netX 50, netX 100 and netX 500 all use either an internal oscillator along with an external crystal or an external oscillator for generating the 25 MHz base clock, which is then stabilized by a PLL which generates all internal Clocks of the chip, except the clock for the internal Real Time Clock (netX 500 only), which is covered in the following subchapter.
The following figure shows the clock circuits for the system clock generation:
Power On Reset
The netX 50, netX 100 and netX 500 provide two inputs for reset signals, the Power On Reset (PORn) and the Reset In (RSTINn). While the use of the RSTINn is optional, the Power On Reset is mandatory. Since the PORn input is equipped with a Schmitt-trigger gate, it could basically be connected to a capacitor (other pin of cap. connected to GND) and a pull-up resistor, however it is strongly recommended to connect this signal to the output of a reset generator with voltage supervision, to make sure, the netX will not be released from reset until the power supplies have reached sufficient and stable levels.
When placing the components during PCB design, the reset source(s) should be placed near the reset inputs of the netX, to keep the traces off the reset signals short. Routing reset signals all over the PCB may result in bad EMC behavior of the design, since ESD may cause undesired resets of the chip.
Experience with several netX designs further has shown, that a 1nF ceramic capacitor connected to GND and PORn, with the capacitor located close to the netX PORn pin, further improves resistivity against ESD.
The following figure shows the standard reset circuits:
RDY-/ RUN-Pins and SYS-LED
The netX 50, netX 100 and netX 500 provide two dedicated I/O pins, that are used for up to three different purposes. These pins are named RDY and RUN and operate as inputs after reset. The first stage bootloader residing in the ROM of the netX chips checks the logic levels on these pins and enters certain boot modes, depending on these levels. After that, the first stage loader configures these pins as outputs, which are used to display status information. Once a firmware is started, it has complete control over these pins and their function may then be completely application specific.
On the netX 50, these pins can also serve a third purpose, which is accessing an I2C security EEPROM, described in the next chapter.
For displaying system status, a system LED (dual LED or two single LEDs) is defined:
|
LED |
Color |
Description |
|
RDY |
Yellow |
netX with operating system is running |
|
RUN |
Green |
User application is running without errors |
Basically, designers could use LEDs with other colors, however it is recommended to use the Hilscher definition (especially when interpreting blink codes for troubleshooting it is helpful if customer and support see the same colors).
netX 50______________________________________________________________________________
______________________________________________________________________________netX 50
netX 100 / 500________________________________________________________________________
________________________________________________________________________netX 100 / 500
Security Memory
The security Memory available for netX controllers, can hold licensing information, MAC addresses and other information. While it is generally recommended to design in this component, it is mandatory for all designs that are to run any Hilscher Master stacks (e.g. PROFIBUS Master, EtherCAT Master). A detailed Application Note explaining the purpose and use of the Security Memory is available on the Hilscher website.
netX 50______________________________________________________________________________
On the netX 50, the security memory must not be connected to the I2C interface! Instead, the RDY and RUN pins are used. All other I2C components used in a netX 50 design must be connected to the I2C interface of the netX 50. The I2C emulation on the RDY and RUN pins is only used by the first stage loader and is not accessible for users.
______________________________________________________________________________netX 50
netX 100 / 500________________________________________________________________________
The netX security memory can be connected parallel to other I2C components as shown in the schematic above. It responds to device addresses starting with 0xB (1010), hence designers have to make sure, that no other connected I2C component uses this address space.
________________________________________________________________________netX 100 / 500
External Memory
Basically, the netX 50, netX 100 and netX 500 provide two different interfaces where firmware memory can be connected to: The (serial) SPI interface and the parallel FLASH/SRAM interface, that shares most of its pins with the SDRAM controller.
When connecting memory components to the parallel FLASH/SRAM/SDRAM interface, designers should always mind the capacitive load that is applied to the interface signals by the memory components. While the memory interface of the netX 100/500 is designed to handle a maximum load capacity of 50pF on data- , address- and DQM3-0 lines and 25pF on all other control signals, these values are reduced to 15pF for all data lines and 10pF for all other memory signals on the netX 50.
Based on the typical capacities of memory components, this lead to the rule of thumb “only one memory component (SDRAM or FLASH) on the netX 50”. Of course, more than one component can be connected, if the above mentioned limits are not exceeded (do not forget the capacity added by the signal traces!).
SPI FLASH
SPI FLASH components consume considerably little space (SO-8 package) on the PCB, while being able to hold large firmware images of 4MB or even greater, hence it is always recommended to add such a FLASH to any design if allowed by board size constraints. Even designs using a parallel FLASH as firmware memory or designs that receive their firmware through the DPM interface from an external host processor, can benefit from an additional serial FLASH that can hold a second stage boot loader or non-volatile user data. Finally it may always simply be left unpopulated if really not used in the final product.
While an SPI Flash can be connected to three different chip select signals (and two different SPI interfaces on the netX 50), it must be connected to chip select 0 (SPI_CS0) and SPI interface 0 (netX 50), when the design is to be able to boot from this SPI Flash.
netX 50______________________________________________________________________________
______________________________________________________________________________netX 50
netX 100 / 500________________________________________________________________________
________________________________________________________________________netX 100 / 500
Parallel FLASH
For large firmware images that come into play with graphical operating systems like Windows CE or for applications executing code directly out of FLASH, the use of parallel FLASH is inevitable. Parallel FLASH connected to the netX may be 8-, 16- or 32 Bit wide, while two 16 Bit components may be paired for 32 Bit wide access.
Though 16 Bit wide components are most common, for performance reasons 32 Bit components should be used when executing code directly out of FLASH.
The netX SRAM/FLASH memory controller provides three different chip select signals (MEM_CS[2:0]), allowing to select three different memory components or pairs of components (two paired 16 Bit FLASHes use a common chip select signal), each with its own set of parameters (timing and bus width).
When the design is to boot from parallel FLASH, chip select 0 must be used for selecting this FLASH.
The memory controller is designed to never “waste” any address lines, regardless of the bus width setting. Hence in 8 Bit mode, address line A0 is used for low and high Byte selection, while in 16 Bit mode A0 selects low and high word and in 32 Bit mode, A0 is simply the LSB of a DWORD address.
For that reason, the data sheet of the desired FLASH component must be consulted, to determine the correct way of hooking up the address lines of the FLASH.
Many (16 Bit-) FLASH components (e.g. TE28F128J..) use address line A0 for low / high Byte selection when operating the component in 8 Bit mode and do not use A0 at all when in 16 Bit mode. Such components must hence have A0 of the FLASH grounded (to prevent floating), while A0 of the netX is connected to A1 of the FLASH, A1 to A2, A2 to A3, etc. The following schematics show an example:
Other FLASH components (e.g. S29GL256P..) always use A0 as the LSB of a Word (16 Bit-) address, hence the address lines of such components must be connected straight forward as shown in the following example schematics:
SDRAM
Most netX applications will require the use of SDRAM, since most of the internal RAM is usually occupied by the standard 64k DPM and buffers, leaving only little space for quite simple applications. For certain slave applications, an alternative to using SDRAM may be the use of parallel FLASH, while the firmware is directly executed out of this FLASH instead of copying the firmware from FLASH to RAM and executing from there (which is the standard situation).
SDRAM components connected to netX may be either 16 Bit or 32 Bit wide, while two 16 Bit components may be paired to allow 32 Bit wide access. Using two 8 Bit components (paired for 16 Bit) or four 8 Bit components (32 Bit) is also possible.
When using SDRAM, 32 Bit wide designs are generally recommended, to make use of the full performance of the memory controller. The use of one 32 Bit wide component instead of two 16 Bit (or four 8 Bit-) components is further recommended, due to easier PCB design and reduced load capacity (two 16 Bit components usually add twice the load to the address and control signals as a comparable 32 Bit component).
Connecting SDRAM to the netX is pretty straight forward, besides address lines A16 and A17, which are used for the bank select signals BA0 and BA1.
